Integrated circuit (IC) devices can be subject to manufacturing variations that can impact performance. In a typical IC device, electrical signals can be transmitted via an interconnect structure formed by multiple metallization layers, separated from one another by interlayer dielectrics (ILDs). Signals can be generated by transistors driving metallization layers between different potentials.
Many fabrication processes utilize chemical-mechanical polishing (CMP) to planarize ILD surfaces. While CMP can improve planarization over other fabrication methods, it can still impart systematic and random thickness variations at the lot, wafer, die and pattern levels. Die level variation in such structures can result in performance and timing differences in the same type of devices. In particular, signal transmission paths can be affected by variations in metal-metal capacitance inherent in an interconnect structure. Differences in metal-metal capacitance can arise from variations in dielectric thickness between metallization lines and/or variations in metal thickness and width. Differences in resistance can also arise from such variations in metal thickness and width.
Active devices (e.g., transistors) may also be subject to some variation in performance. For example, uncontrollable manufacturing variations can result in “fast” transistors and “slow” transistors. Fast transistors can provide faster driving capability than slow transistors. Such fast vs. slow variations can be systematic, i.e., they can affect the mean value of performance parameters.
These and other variations can result in IC devices having differing performance limits. Conventionally, timing paths can be designed with sufficient margin to be adequate for a slowest case. This can require large signal driving devices and increased power consumption, as well as increased design effort. For some very high performance IC devices, such variations can present a limit to device speed and/or reliability.